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MAX6707LKA-T

MAX6707LKA-T Power Supply Monitor, Active-Low Reset

MPNMAX6707LKA-T
End of Life

Analog Devices MAX6707LKA-T Power Supply Monitor, Active Low Reset, Open Drain Output, SOT-23-8, 120ms Minimum Reset Timeout, 4.63V Threshold, -40°C to 125°C.

$1.84Ref. price · indicative, final on quote
PackagingSOT-23-8
RoHSRoHS non-compliant
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

MAX6707LKA-T specifications
ParameterValue
TypePower Supply Monitor
MountingSurface Mount
Voltage - threshold4.63V
Number of voltages monitored2
Operating temperature-40°C ~ 125°C (TA)
ResetActive Low
OutputOpen Drain or Open Collector
PackageBulk
Reset timeout120ms Minimum
CaseSOT-23-8

Product details

Dual-voltage supervisor with 4.63V fixed threshold

The MAX6707LKA-T is a power supply monitor from Analog Devices that supervises up to two voltage rails, with one threshold fixed at 4.63V. The active-low, open-drain reset output asserts when either monitored voltage drops below its threshold and holds for a minimum of 120ms after all rails return to tolerance — long enough for the system oscillator and core supply to settle before the CPU is released from reset.

Industrial temperature range and small-footprint package

Housed in an 8-pin SOT-23 package, the footprint is 2.9 mm × 1.6 mm — small enough for space-constrained designs like sensor nodes or handheld instruments. The surface-mount package is compatible with standard reflow profiles; no special handling beyond normal MSL precautions.

Active lifecycle, RoHS non-compliant — sourcing note

Note that this part is RoHS non-compliant. For designs requiring RoHS compliance, a lead-free variant or an exemption may be needed. Confirm the regulatory requirement for your target market before committing the BOM line.

Frequently asked questions

What is the reset timeout of MAX6707LKA-T?

The reset timeout is a minimum of 120ms. After all monitored voltages rise above their thresholds, the reset output remains asserted for at least 120ms before releasing the CPU.