Two-rail supervisor in a four-pin SC-70
Reset timeout is a minimum of 140ms, long enough to cover most MCU/FPGA boot sequences without external timing components. The open-drain output lets the reset line be shared across multiple supervisors or pulled up to a different voltage than the monitored rails.
Housed in a 4-pin SC-70 (SOT-343) package, it occupies minimal board area.
Note the RoHS non-compliant marking — this is the legacy tin-lead finish version. If your assembly line is RoHS-exempt (military, aerospace, or medical with exemption 7a), this is the correct variant. For standard RoHS builds, verify the lead-free suffix (e.g., MAX6389XS44D3+T) is the intended order code.
