140ms reset timeout — sizing the power-up sequence
For most MCUs and FPGAs, this is long enough to cover the power-good assertion of a typical LDO or DC-DC converter. If your design has a slow-start converter or a large bulk capacitor on the rail, verify that the 140ms window is sufficient — otherwise the processor may begin operation before the supply is fully stable.
For new designs or ongoing production, this part is a straightforward BOM line to maintain — no last-time-buy planning or substitution needed.