The output is active-low, push-pull/totem-pole, which directly drives the reset input of most MCUs, FPGAs, and SoCs without an external pull-up resistor.
Reset timeout — 1ms minimum
The 1ms minimum reset timeout holds the processor in reset for at least 1 millisecond after the supply crosses the threshold on the way up. That window covers oscillator startup, PLL lock time, and regulator ramp for most small MCUs and FPGAs. If your design uses a fast-boot processor or a multi-rail sequencer, verify that 1ms is long enough to clear all power-good flags before the CPU starts executing code.
It is ROHS3 compliant. No LTB window or obsolescence risk to track for this order code.