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Analog Devices MAX6355RWUT-T — Discrete Semiconductors
Analog Devices

MAX6355RWUT-T Multi-Voltage Supervisor, 3-Channel SOT-23-6

MPNMAX6355RWUT-T
End of Life

Maxim Integrated MAX6355RWUT-T multi-voltage supervisor, 3-channel, active-low open-drain reset, 100ms min reset timeout, SOT-23-6 package, -40°C to 85°C.

$1.84Ref. price · indicative, final on quote
MAX6355RWUT-T datasheet
PackagingSOT-23-6
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

MAX6355RWUT-T Technical Specifications
ParameterValue
TypeMulti-Voltage Supervisor
Mounting typeSurface Mount
Voltage - threshold1.67V, 2.63V, Adj
Number of voltages monitored3
Operating temperature-40°C ~ 85°C (TA)
ResetActive Low
OutputOpen Drain or Open Collector
PackageBulk
Reset timeout100ms Minimum
CaseSOT-23-6

Product details

Temperature range and environment

Rated for -40°C to 85°C ambient, this part is suited for industrial control, telecom infrastructure, and outdoor equipment where the enclosure sees temperature swings but not under-hood extremes. Not qualified for automotive or military extended-temperature applications.

Lifecycle and compliance

The MAX6355RWUT-T is listed as active in production — no end-of-life notice or last-time-buy window is in effect. The key compliance flag is RoHS non-compliance. For designs that require RoHS conformity, this part will not pass incoming inspection in EU-regulated markets.

Frequently asked questions

Is MAX6355RWUT-T RoHS compliant?

No, the MAX6355RWUT-T is listed as RoHS non-compliant. It contains lead and cannot be used in RoHS-regulated production without an exemption.

What does the 100ms minimum reset timeout mean for my design?

The 100ms minimum reset timeout ensures the supervisor holds the reset line low for at least 100ms after all monitored voltages rise above their thresholds. This gives the system's power-on reset circuitry and oscillators time to stabilize before the processor or FPGA begins executing code.