20-bit R-2R DAC with 1.5 µs settling — the precision ceiling for a single-supply 5 V signal chain
The MAX5719AGSD+ is a single-channel, 20-bit voltage-output DAC built on an R-2R ladder architecture. It resolves 1,048,576 steps across a 0 V to Vref output range, with the reference supplied externally. Settling time is 1.5 µs typical to ±1 LSB — fast enough for closed-loop servo updates or waveform generation in the low-kHz band without starving the downstream ADC of acquisition time. The SPI/DSP-compatible serial interface operates at clock rates up to 50 MHz (per the family datasheet), allowing a full 20-bit frame to load in under 0.5 µs and leaving the remaining settling budget for the analog output stage.
Linearity and temperature range — what ±1 LSB INL/DNL means for a 20-bit system
Integral and differential nonlinearity are both specified at ±1 LSB maximum. At 20 bits, 1 LSB is roughly 4.8 µV on a 5 V reference — the INL error stays within that window across the full output range, so the transfer curve never deviates by more than one code from the ideal straight line. The ±1 LSB linearity is guaranteed across this band, not just at 25°C — important for a calibration DAC that must hold accuracy over a hot factory floor or an outdoor enclosure.
Single-supply rail and package — board-fit constraints
There is no separate DVDD — the same 5 V plane feeds the R-2R ladder and the SPI input shift register. A single decoupling cap at each supply pin (0.1 µF ceramic plus 10 µF bulk) is the standard recommendation. A board already laid out for a 14-SOIC DAC can accept the MAX5719AGSD+ without a respin, provided the supply voltage and reference topology match.