12-bit voltage-output DAC with R-2R architecture
It uses an R-2R ladder architecture for the DAC core, which keeps the die small and the cost predictable. The output is voltage-buffered, so it can drive a moderate load directly without an external op-amp. Typical settling time to ½ LSB is 25 µs, which sets the maximum update rate at roughly 40 kHz — fine for set-point control, trim pots, and audio-level adjustment, but not for waveform synthesis above the audio band. Data interface is SPI, which is the standard for board-level DACs. The reference is external, so the output full-scale range tracks whatever reference voltage you supply (up to the analog supply rail).
The 8-SOIC package is a standard footprint — no surprises for the pick-and-place line or the reflow profile. Surface-mount only; no through-hole variant exists for this code.
Linearity and monotonicity
INL and DNL are both specified at ±1 LSB maximum. The transfer function is guaranteed monotonic.
That means no last-time-buy clock is ticking, no broker scavenger hunt required.