16Kbit NVSRAM with 150 ns access — the scorch-mark tells you
The DS1220AB-150IND+ is a 16Kbit Non-Volatile SRAM organized as 2K x 8 bits, with a 150 ns access time and a parallel memory interface. Housed in a 24-pin EDIP (0.600" wide, 15.24 mm pitch), it's a through-hole part that drops into legacy sockets or new designs where a DIP footprint is still the standard.
Supply rail and timing — what fits the bus
The 150 ns access time is the window the controller waits for data to appear on the bus — if your microcontroller or ASIC expects a faster handshake, this part won't meet the timing budget without wait states. Write cycle time matches the read access at 150 ns, so the bus protocol is symmetric — no separate penalty for writes. The parallel interface is straightforward: address, data, chip enable, write enable, output enable. No multiplexing, no serial clock.