The ADP1754ACPZ-1.1-R7 is a single-output LDO that holds a fixed 1.1V output within regulation up to 1.2A continuous. That current ceiling covers the core supply of many mid-range FPGAs, SoCs, or DDR3 VTT termination rails — anything that pulls under an amp on a 1.1V bus. The quiescent current sits at 800 µA typical, with a maximum supply current of 1.4 mA. For a battery-powered sensor node that spends most of its time in a low-power state, that Iq is the floor the system sees when the load is light — it matters for standby budget. The 200 mV dropout at full load means the input must stay above 1.3V to keep the 1.1V output in regulation — a 3.3V rail with 5% tolerance leaves plenty of headroom.
Package and thermal — the exposed pad is non-negotiable
The 16-lead LFCSP (4x4 mm) has an exposed pad on the bottom. That pad is the primary thermal path — at 1.2A output, the power dissipation is roughly 0.6W with a 1.5V drop, and without soldering the pad to a copper plane on the PCB, the junction temperature will exceed the 125°C rating under load. The datasheet layout note calls for multiple vias under the pad to a ground plane. The package is surface-mount only — no through-hole equivalent. The tape-and-reel option is the volume format; cut tape is available for prototype or single-board repair quantities.
Protection set — reverse polarity and UVLO are unusual on an LDO
Beyond the standard over-current and over-temperature shutdown, this regulator includes reverse polarity protection and an under-voltage lockout (UVLO). The reverse polarity block means the part survives a swapped input connection without an external Schottky diode in series — that diode's forward voltage would otherwise eat into the dropout margin. The UVLO holds the output off until the input rises above a threshold, preventing the regulator from trying to regulate from a sagging rail. The control set includes Enable, Power Good, and Soft Start. Power Good is an open-drain flag that asserts when the output is within regulation — useful for sequencing a downstream DC-DC converter or holding a microcontroller in reset until the 1.1V rail is stable. Soft Start limits inrush current during startup, which matters when the output capacitor bank is large.