RF local oscillator in a 16-pin TSSOP
It accepts CMOS or TTL reference inputs and delivers a clock output, with a 2:1 input-to-output ratio and differential output capability.
The 3 GHz maximum frequency covers the 2.4 GHz ISM band, the 2.1-2.7 GHz cellular bands, and most satellite downlinks below 3 GHz. If your VCO or reference runs above that, this part will not lock — you need the ADF4113 or a higher-frequency PLL. The divider/multiplier is set to divide only (no on-chip multiplication), so the reference frequency must be chosen to match the loop bandwidth and channel spacing.
The CMOS/TTL-compatible inputs mean you can drive it from a 3.3 V microcontroller or an FPGA without level shifters — saves a couple of resistors and a BOM line. The output is a clock signal, not a sine wave, so it drives the charge pump and loop filter directly.
Industrial temperature — outdoor and factory gear
No commercial-grade limitation here — if the enclosure is unheated or the radio sits on a rooftop, the ADF4118BRUZ keeps the PLL locked across the full range.
Package and rework — 16-TSSOP, no hot air needed
It reflows with a standard profile and can be hand-soldered with a fine-tip iron and flux — no hot-air station required for a field swap. The orientation is obvious from the pin-1 chamfer, and the 0.65 mm pitch is manageable with tweezers and a steady hand.
If you need a second source, ADI's ADF4118 family has no direct pin-compatible clone from another manufacturer — the part is single-sourced, so qualifying an alternate requires a different PLL architecture.