0.83 ns propagation delay — the timing budget decider
The ADCMP564BRQZ: The 0.83 ns max propagation delay sets the upper bound on the comparator's throughput in a sampled-data system — at that delay the output settles before the next latch clock edge, so the effective toggle rate is limited by the setup-time window of the downstream logic, not the comparator itself.
Active lifecycle — no end-of-life pressure on the BOM
ROHS3 compliant, so it passes the EU material restriction gate without an exemption letter. No REACH or UL cert appears in the spec record, but the RoHS status covers the common compliance check for a comparator in this package class.
Pin-to-pin alternate: ADCMP562BRQZ
The ADCMP562BRQZ shares the same 20-QSOP footprint, same ±1 mV hysteresis, same 0.83 ns propagation delay, and same 80 dB CMRR / 85 dB PSRR typicals. The only parametric delta is the output type: the ADCMP564BRQZ carries Complementary, Differential, ECL, Open-Emitter outputs, while the ADCMP562BRQZ lists Complementary, Differential, Open-Emitter, PECL — PECL vs ECL logic levels. If the downstream receiver expects PECL (positive-referenced ECL) rather than standard ECL, the ADCMP562BRQZ drops in without a board spin.
The 80 dB CMRR and 85 dB PSRR typicals hold across this range — the datasheet typical curves show less than 3 dB degradation at the temperature extremes, so the common-mode rejection stays intact for precision threshold detection.