Active production — 12-bit TxDAC® with 35 ns settling
The AD9752ARUZ: The parallel data interface accepts a full 12-bit word in one clock cycle, so the update rate is limited by the host bus cycle, not the DAC's internal latency.
Supply rails and reference flexibility
The reference can be driven externally or sourced from the internal bandgap — the choice trades absolute accuracy against board space. Differential current outputs give a 2× signal swing into a transformer or differential op-amp front end, which improves common-mode rejection in the analog path. The current-source architecture means the output compliance range must be respected — the voltage at the IOUT pins should stay within 0 V to 1.25 V for rated linearity.
INL/DNL and the 28-TSSOP footprint
Integral nonlinearity is ±0.5 LSB typical, differential nonlinearity ±0.25 LSB — this is a monotonic part with no missing codes across the full 12-bit range. The tube packaging is the standard factory format for this part; if your pick-and-place line runs tape-and-reel, the AD9752ARUZRL7 variant is the reeled version — same die, same electricals, different shipping media.
Compliance and sourcing posture
ROHS3 compliant per the manufacturer's declaration — no exemptions beyond the standard RoHS deadline substances. Active lifecycle status means the part is still in the catalog and available through authorized distribution; no last-time-buy window or successor part has been announced.