16-bit, 1 MSPS SAR — no pipeline latency
The AD7980ARMZRL7 is a 16-bit successive-approximation-register (SAR) ADC from the PulSAR® family, sampling at 1 MSPS. The SAR architecture means every conversion result corresponds to a single snapshot of the input — there is no pipeline delay to manage in a multiplexed or closed-loop control system. The pseudo-differential input accepts a single-ended signal referenced to a common-mode voltage, which simplifies the front-end drive compared to a fully differential input while still rejecting some common-mode noise. The external reference (REF) pin lets the user set the full-scale range to match the sensor or signal-conditioning output swing.
Single 2.5 V supply, SPI/DSP interface
Both the analog and digital supply rails run from 2.375 V to 2.625 V — a single 2.5 V rail powers the core and the digital I/O. That eliminates a second regulator and simplifies the power-tree layout. The SPI/DSP-compatible serial interface uses three wires (SCK, SDI, SDO) plus a CNV pin to initiate conversions. The bus runs at clock rates up to 50 MHz, so the 16-bit readout fits within the 1 µs conversion cycle without stretching the serial clock. The tape-and-reel packaging (AD7980ARMZRL7 suffix) suits automated pick-and-place assembly.
Lifecycle status is active, with ROHS3 compliance — no end-of-life notice or material-restriction gap for new designs.