Key ratings — what they mean for the BOM
120 MHz core speed: that is the PWM-update and ADC-trigger rate for a 16 kHz current loop with margin. At this clock, the C28x pipeline executes a single-cycle multiply-accumulate, so the 17x12b ADC can be oversampled and filtered in firmware without a separate FPGA. 512 KB Flash (256K x 16) is sized for a full AUTOSAR or motor-control application layer plus calibration tables. The 50K x 16 RAM covers the stack, DMA buffers, and a modest data logger. No EEPROM on die — the Flash can emulate it via the onboard ECC and wear-leveling if the application note is followed. 17 analog inputs with 12-bit resolution and three 12-bit DACs: enough for a three-phase motor current feedback plus resolver or encoder position sensing without external muxes. The DACs can drive the reference inputs of companion gate-driver ICs directly.