STM32F469AGY6TR — STM32F4 Cortex-M4 1MB Flash 384KB RAM 180MHz WLCSP
STMicroelectronics STM32F4 series, STM32F469AGY6TR, ARM Cortex-M4 32-bit single-core 180MHz, 1MB Flash, 384KB RAM, 24-channel 12-bit ADC, Ethernet MAC, CANbus, USB OTG, 114 I/O, 168-WLCSP (4.89×5.69mm), surface mount, 1.7–3.6V supply, -40°C to 85°C operating temperature, Tape & Reel.
- 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
- Date & lot codes on quoteStated per line before you commit; label photos on request.
- MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
- PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.
Specifications
| Parameter | Value |
|---|---|
| Series | STM32F4 |
| Mounting type | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 1.7V ~ 3.6V |
| Operating temperature | -40°C ~ 85°C (TA) |
| Speed | 180MHz |
| Package | Tape & Reel (TR) |
| RAM size | 384K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT |
| Connectivity | CANbus, EBI/EMI, Ethernet, I²C, IrDA, LINbus, SAI, SDIO, SPI, UART/USART, USB, USB OTG |
| Number of i (O) | 114 |
| Core processor | ARM® Cortex®-M4 |
| Case | 168-UFBGA, WLCSP |
| Data converters | A/D 24x12b; D/A 2x12b |
| Program memory size | 1MB (1M x 8) |
Frequently asked questions
Can the 168-UFBGA WLCSP be replaced on a live board?
No. The 168-ball WLCSP at 0.5mm pitch and 4.89×5.69mm body requires controlled preheat, hot-air or IR rework, and X-ray inspection to verify joint integrity — not a hot-swap scenario. Full power-down is mandatory. If you need field replaceability, the board goes to a rework bench; do not attempt this package swap with a soldering iron on a live production line.
Does the STM32F469AGY6TR's Ethernet MAC support IEEE 1588 PTP timestamping?
PTP hardware timestamping support is not listed in the connectivity ledger for this part. The Ethernet MAC described is present and functional for standard TCP/IP and EtherNet/IP stacks, but hardware time synchronization for sub-microsecond precision would require verification against the full datasheet — it is not a confirmed ledger-level feature.