STM32F446VET6 STMicroelectronics 32-bit MCU, 180MHz, 512KB Flash, LQFP-100
STMicroelectronics STM32F4 series, 32-bit ARM Cortex-M4 single-core MCU running at 180MHz with 512KB Flash and 128KB SRAM; 81 I/O, USB OTG, CAN, SPI/UART, 16-channel 12-bit ADC, 2-channel 12-bit DAC; 100-LQFP surface-mount package rated -40°C to 85°C on 1.7–3.6 V supply; lifecycle: end-of-life.
- 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
- Date & lot codes on quoteStated per line before you commit; label photos on request.
- MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
- PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.
Specifications
| Parameter | Value |
|---|---|
| Series | STM32F4 |
| Mounting type | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 1.7V ~ 3.6V |
| Operating temperature | -40°C~85°C(TA) |
| Speed | 180MHz |
| Package | Tray |
| RAM size | 128K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | Brown-out Detect/Reset, DMA, I²S, LVD, POR, PWM, WDT |
| Connectivity | CANbus, EBI/EMI, I²C, IrDA, LINbus, SAI, SD, SPDIF-Rx, SPI, UART/USART, USB, USB OTG |
| Number of i (O) | 81 |
| Core processor | ARM® Cortex®-M4 |
| Case | 100-LQFP |
| Data converters | A/D 16x12b; D/A 2x12b |
| Program memory size | 512KB (512K x 8) |
Frequently asked questions
What are the core specs that drive MCU selection for this part?
180MHz ARM Cortex-M4, 512KB Flash / 128KB SRAM, 81 I/O in 100-LQFP, 1.7–3.6 V supply, -40°C to 85°C operating range, USB OTG + CAN + SDIO + SAI, 16-channel 12-bit ADC and 2-channel 12-bit DAC.
Is the STM32F446VET6 moisture-sensitive, and what is its floor-life limit?
The specific MSL rating and floor-life limit for the 100-LQFP tray are not in the available record. Standard JEDEC J-STD-020 MSL3 (peak reflow 260°C) applies to most LQFP packages in this size range from ST, but confirm against the ST MSL document for the specific date code before triggering a first-bake protocol on stored spares.