Skip to main content
STMicroelectronics M24C64-WDW6TP — Memory (DRAM / SRAM / Flash / EEPROM)

M24C64-WDW6TP — STMicroelectronics 64Kbit I²C EEPROM, TSSOP-8, NRND

MPNM24C64-WDW6TP
NRND

STMicroelectronics M24C64-WDW6TP, 64Kbit I²C EEPROM, 8-TSSOP (4.40 mm), 2.5–5.5 V supply, 1 MHz clock, 450 ns access, 5 ms write cycle, −40°C to 85°C, NRND.

$0.3000Ref. price · indicative, final on quote
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

M24C64-WDW6TP Technical Specifications
ParameterValue
Memory typeNon-Volatile
Mounting typeSurface Mount
Voltage2.5V ~ 5.5V
Frequency1 MHz
Memory interfaceI²C
Operating temperature-40°C ~ 85°C (TA)
PackageTape & Reel (TR) Cut Tape (CT)
TechnologyEEPROM
Access time450 ns
Memory size64Kbit
Memory formatEEPROM
Case8-TSSOP (0.173\", 4.40mm Width)
Memory organization8K x 8
Write cycle time - word, page5ms

Frequently asked questions

What is the I²C address range for the M24C64-WDW6TP, and are A0/A1/A2 pins available on the TSSOP-8?

The device uses 7-bit I²C addressing with hardware-selectable A0/A1/A2 pins — verify pin availability on the TSSOP-8 pinout before assuming addressability on a shared bus. The 1 MHz Fast-Mode Plus clock ceiling is backwards-compatible with 400 kHz hosts.

Can the M24C64-WDW6TP drop in as a replacement for a legacy 24C64 device on an existing board?

The same TSSOP-8 footprint, I²C interface, and 2.5–5.5 V supply range make it mechanically and electrically compatible in most legacy designs, but confirm the exact I²C address configuration and pull-up resistor values against the existing board — the 1 MHz clock ceiling is a slight upgrade over older 100/400 kHz parts and should not cause compatibility issues.

What are the key timing specs that affect write-cycle throughput in the application?

The 5 ms write-cycle per word or page governs how long the bus is held during a write operation; the 450 ns access time sets the read latency. For page-write bursts, the 64-byte page boundary of the 8K × 8 organization limits how much you can pack into a single write cycle before a roll-over occurs at the page boundary.