0.45 ns access time — the speed floor for cache-line fill
The Renesas R1QEA7218ABG-19IB0 is a standard SRAM organized 4Mx18 with a 0.45 ns access time — this is the cycle-limiting path for a read operation, not the bus clock. A 0.45 ns access means the data appears at the outputs within 450 ps of the address strobe, setting the minimum cycle time for the memory bus at roughly 2.2 GHz if the controller can sustain back-to-back reads without wait states. The part ships in Bulk packaging, which typically means loose trays or tubes rather than tape-and-reel — a factor for pick-and-place setup if the line expects reeled components.
Active production and compliance status
RoHS compliance is confirmed as ROHS3 Compliant, covering the full ten restricted substances including the four phthalates added under EU 2015/863.