85 MHz SPI — timing margin for the host
The 85 MHz SPI clock is the headline speed. At this rate the serial interface can sustain read throughput roughly in the tens of megabytes per second, depending on the host's SPI peripheral and the command overhead. That is fast enough for direct code execution (XiP) in many MCUs and for FPGA configuration loading without stalling the boot sequence. The page write cycle takes 5 ms, and the byte/word write takes 8 µs — the page time dominates when you are filling a full page buffer.
Industrial temperature and active lifecycle
ROHS3 compliant, no exemption issues for EU markets.
The 8-VDFN (6x8 mm) exposed-pad package is a surface-mount footprint. No through-hole option exists for this density.