183 MHz clock, 3.3 ns access — speed-grade fit
The 71V35761S183PFI: With a 183 MHz clock frequency and 3.3 ns access time, this synchronous SDR SRAM delivers the throughput needed for high-speed cache buffers, network packet memory, or DSP scratchpad — the access time sets the minimum read cycle window, and the clock rate governs the burst transfer ceiling. Organised as 128K x 36 bits (4.5 Mbit total), the 36-bit data word matches a 32-bit bus with parity or ECC overhead, or a 36-bit wide FIFO path without packing cycles.
RoHS non-compliant — compliance check
Marked RoHS non-compliant per the manufacturer's declaration — the lead finish likely exceeds the 0.1 % threshold. This matters for EU RoHS-exempt applications (military, aerospace, some industrial spares) but will flag in a standard RoHS BOM scan.