3-to-8 line decoder/demultiplexer for address and chip-select
The 74LV138D/S400118: It decodes three binary address inputs into eight mutually exclusive active-low outputs, with three enable inputs (two active-low, one active-high) for cascading or gating.
Sourcing posture for this order code
This order code is a standalone variant within the NXP logic portfolio. No direct second-source or cross-reference is listed.