20 ns PAL-type CPLD in PLCC-28
The GAL22V10-20LVI is a 20 ns propagation-delay PAL-type electrically erasable programmable logic device in a 28-lead PLCC package. The 20 ns speed grade sets the maximum combinatorial path delay from input through the AND-OR array to registered output — a ceiling that governs the clock rate in a synchronous design. The PLCC-28 (PQCC28) footprint is a JEDEC-standard 0.050-inch pitch, 11.5 mm square body.