Infineon (formerly Cypress) lists the CY7C057V-12AXC as obsolete.
32K x 36 dual-port SRAM, 12 ns access
This is a 1.152 Mbit dual-port asynchronous SRAM organized as 32K words by 36 bits. The 12 ns access time and 12 ns write cycle time mean the part can complete a read or write operation in a single 83 MHz clock cycle — relevant for shared-memory designs where two controllers or processors need low-latency access to the same data buffer. The parallel memory interface connects directly to a standard SRAM bus without protocol overhead.
144-LQFP package — board-fit note
Supplied in a 144-lead LQFP tray, with the supplier device package specified as 144-TQFP (20x20). The 0.5 mm pitch LQFP footprint is a standard surface-mount package — the 20x20 mm body requires a reflow profile consistent with JEDEC MSL ratings typical for this class.