Cypress CY7C057V-12AXC Dual-Port SRAM, 1.152Mbit 32Kx36, 12ns
MPNCY7C057V-12AXC
Obsolete
Cypress (now Infineon) CY7C057V-12AXC, 1.152Mbit dual-port asynchronous SRAM, 32K×36 organization, 12 ns access/write cycle, 3V–3.6V supply, 144-LQFP tray, 0°C–70°C.
$139.9100Ref. price · indicative, final on quote
StockContact for availability
MOQ1 pcs
- 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
- Date & lot codes on quoteStated per line before you commit; label photos on request.
- MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting type | Surface Mount |
| Voltage | 3V ~ 3.6V |
| Memory interface | Parallel |
| Operating temperature | 0°C~70°C(TA) |
| Package | Tray |
| Technology | SRAM - Dual Port, Asynchronous |
| Access time | 12 ns |
| Memory size | 1.152Mbit |
| Memory format | SRAM |
| Case | 144-LQFP |
| Memory organization | 32K x 36 |
| Write cycle time - word, page | 12ns |
Frequently asked questions
What are the timing constraints for interfacing this SRAM to a 33 MHz bus or 50 ns wait-state microcontroller?
The 12 ns access time and 12 ns write cycle time are faster than a 33 MHz bus cycle (~30 ns), leaving comfortable margin for FPGA read-FSM timing closure. The 50 ns wait-state microcontroller bus easily satisfies the SRAM's write pulse width requirement. No byte-enable or bank-select details are available in the current evidence — confirm against the full Cypress datasheet for the 32K×36 word strobe architecture.