The Infineon CY7C25652KV18-400BZC is a 72 Mbit QDR II+ synchronous SRAM organised as 2M x 36. It clocks at 400 MHz on a parallel interface, running from a 1.7 V to 1.9 V supply. The QDR II+ architecture eliminates bus-turnaround dead cycles, delivering back-to-back read and write throughput at the full clock rate — critical for high-bandwidth packet buffers in networking switches and for FPGA-based data accelerators that cannot tolerate a dead cycle between transactions.
Housed in a 165-FBGA (13x15 mm), the package footprint is shared across the CY7C25652 density family.
