72 Mbit QDR II+ SRAM at 450 MHz — bus-width and timing fit
The CY7C2564XV18-450BZC is a 72 Mbit synchronous SRAM using the QDR II+ architecture, organized as 2M words by 36 bits.

Cypress QDR II+ synchronous SRAM, CY7C2564XV18-450BZC, 72 Mbit organized 2M x 36, 450 MHz clock, parallel interface, 1.7–1.9 V supply, 165-FBGA (13x15 mm) surface mount, 0–70 °C.
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 1.7V ~ 1.9V |
| Clock frequency | 450 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Bulk |
| Technology | SRAM - Synchronous, QDR II+ |
| Memory size | 72Mbit |
| Memory format | SRAM |
| Case | 165-LBGA |
| Memory organization | 2M x 36 |
The CY7C2564XV18-450BZC is a 72 Mbit synchronous SRAM using the QDR II+ architecture, organized as 2M words by 36 bits.
Yes, the CY7C2564XV18-450BZC and CY7C2565XV18-633BZC share the same 165-FBGA (13x15 mm) footprint, 72 Mbit density, 2M x 36 organization, and 1.7–1.9 V supply. The pinout is compatible, so a board designed for the 633 MHz part will physically accept the 450 MHz part. The trade-off is a lower peak bandwidth — verify that your controller timing can operate at 450 MHz and that the lower throughput meets your application's worst-case data rate.