366 MHz QDR II+ SRAM for high-throughput buffers
It runs at a 366 MHz clock, delivering back-to-back read and write operations on separate data ports — no bus-turnaround dead cycles. The 4M x 18 organization gives you 18-bit word widths, useful for applications that carry parity or sideband data alongside the main payload. Typical deployment is in high-performance networking gear, telecom line cards, and compute accelerators where deterministic latency and sustained bandwidth matter more than density.
At 366 MHz, this part moves 18 bits per clock edge on both read and write ports simultaneously. The QDR II+ architecture eliminates turnaround cycles.
