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Cypress Semiconductor Corp CY7C1471BV25-133AXI — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1471BV25-133AXI 72Mbit NoBL SRAM, 133 MHz

MPNCY7C1471BV25-133AXI
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Infineon CY7C1471BV25-133AXI, NoBL™ series, 72Mbit synchronous SRAM, 2M x 36 organization, 133 MHz clock, 6.5 ns access time, parallel interface, 2.5V supply, 100-TQFP, -40°C to 85°C.

$152.5500Ref. price · indicative, final on quote
Cypress Semiconductor Corp CY7C1471BV25-133AXI datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1471BV25-133AXI specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage2.375V ~ 2.625V
Clock frequency133 MHz
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageBulk
TechnologySRAM - Synchronous, SDR
Access time6.5 ns
Memory size72Mbit
Memory formatSRAM
Case100-LQFP
Memory organization2M x 36

Product details

72Mbit NoBL SRAM for high-throughput data paths

Its NoBL (No Bus Latency) architecture eliminates the dead cycle between read and write operations, sustaining back-to-back throughput at the full 133 MHz clock rate. The 6.5 ns access time keeps address-to-data latency tight enough for network packet buffers, telecom line cards, and image frame stores where every clock cycle counts. The 2.5V supply rail (2.375V to 2.625V) aligns with low-voltage core logic, saving a regulator step in mixed-voltage designs.

The 100-TQFP (14x20 mm) package is surface-mount only.

Frequently asked questions

What is the NoBL series on this component?

NoBL stands for No Bus Latency, a Cypress (now Infineon) architecture that allows back-to-back read and write operations without dead cycles, maximizing throughput on the synchronous bus.

Will CY7C1471BV25-133AXI drop into a board designed for CY7C1470V25-200BZI?

Both parts share the same 72Mbit density, 2M x 36 organization, 2.5V supply, and 100-TQFP package, so the footprint is identical. However, the 133 MHz part has a slower access time (6.5 ns vs 3 ns) — verify timing closure at the lower speed grade before substituting.