72Mbit NoBL synchronous SRAM for high-throughput cache
The Cypress CY7C1470BV33-167AXI is a 72Mbit synchronous SRAM from the NoBL™ family, organized as 2M words by 36 bits. It clocks at 167 MHz with a 3.4 ns access time, eliminating dead bus cycles on back-to-back reads and writes — a fit for network processor look-aside caches, FPGA block-RAM expansion, or telecom line-card buffers where every clock edge carries data.
The commercial-temperature variant (CY7C1470BV33-200AXC) runs at 200 MHz with 3 ns access but is rated 0°C to 70°C only — not suitable for the same outdoor or unvented enclosure. For a BOM that needs the industrial range, the -167AXI is the correct speed grade.
100-TQFP footprint and supply rail
The NoBL™ architecture means the controller can assert a new address every clock cycle without inserting idle cycles for read-to-write turnaround. This is the key difference from a pipelined synchronous SRAM that inserts one dead cycle on bus direction change.