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AMD (Xilinx) XC3S5000-4FGG1156C — FPGA / CPLD & Programmable Logic

Xilinx XC3S5000-4FGG1156C Spartan-3 FPGA, 5M Gates, 633 I/O

MPNXC3S5000-4FGG1156C
Active

Xilinx Spartan®-3 series FPGA, XC3S5000-4FGG1156C, 5,000,000 gates, 74,880 logic cells, 633 user I/O, 1.14 V core, 1,916,928 bit block RAM, surface-mount Bulk package.

$256.11Ref. price · indicative, final on quote
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MOQ1 pcs
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Specifications

XC3S5000-4FGG1156C Technical Specifications
ParameterValue
SeriesSpartan®-3
Mounting_typeSurface Mount
Package_typeBulk
Number of i (O)633
Total ram bits1916928
Product_statusActive
Number of gates5000000
Supply_voltage_v1.14
Number of labs (Clbs)8320
Number of logic elements (Cells)74880

Product details

Spartan-3 FPGA — 5 million gates for medium-density logic

The Xilinx XC3S5000-4FGG1156C is a Spartan®-3 series FPGA packing 5,000,000 gates and 74,880 logic cells in a surface-mount package. With 633 user I/O and 1,916,928 bits of block RAM, it handles moderate digital designs — think soft-core processor plus peripheral glue, video line buffers, or multi-channel data acquisition — without reaching for a larger die. Core supply runs at 1.14 V, which keeps dynamic power in check for the gate count.

633 I/O — what it means for the board layout

633 user I/O pins are available. Each I/O bank operates at its own Vccio, supporting multiple voltage domains.

Active lifecycle — no LTB pressure

The XC3S5000-4FGG1156C carries an Active product status. No official successor is listed.

Frequently asked questions

What is the XC3S5000-4FGG1156C datasheet and pinout?

The datasheet and pinout for the XC3S5000-4FGG1156C are available from Xilinx (now AMD) as part of the Spartan-3 FPGA documentation. The part has 633 user I/O arranged in multiple banks with configurable Vccio levels. The FGG1156 package uses a 1.0 mm pitch BGA with 1156 balls.

How many I/O pins does XC3S5000-4FGG1156C have and what are the voltage levels?

The XC3S5000-4FGG1156C provides 633 user I/O pins. The core operates at 1.14 V, while I/O banks can be independently set to 3.3 V, 2.5 V, 1.8 V, or 1.5 V depending on the Vccio supply connected to each bank.