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AMD (Xilinx) PALCE610H-20/BLA — Discrete Semiconductors

PALCE610H-20/BLA PAL Device, 20 ns, 24-CDIP, Active

MPNPALCE610H-20/BLA
End of Life

PALCE610H-20/BLA, Electrically Erasable PAL Device, 20 ns speed, 4.75V ~ 5.25V supply, 24-CDIP (0.300", 7.62mm) Through Hole package, Bulk.

$58.14Ref. price · indicative, final on quote
Packaging24-CDIP (0.300", 7.62mm)
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

PALCE610H-20/BLA Technical Specifications
ParameterValue
Mounting typeThrough Hole
Programmable typePAL
Voltage - input4.75V ~ 5.25V
Speed20 ns
PackageBulk
Case24-CDIP (0.300\", 7.62mm)

Product details

20 ns propagation delay — what it means for the bus

The PALCE610H-20/BLA: Electrically erasable PAL device with 20 ns propagation delay. Supply range is 4.75 V to 5.25 V.

Hermetic 24-CDIP — deployment context

The 24-CDIP (0.300", 7.62 mm) ceramic package is through-hole only, with a hermetic seal rated for military temperature range and high-reliability environments — avionics, missile guidance, satellite, downhole instrumentation. The ceramic body handles wider thermal cycling than plastic DIP, but the part is not surface-mount; board space and assembly process must accommodate a through-hole footprint. Bulk packaging means loose tubes, not tape-and-reel.

Frequently asked questions

Where can I buy PALCE610H-20/BLA?

PALCE610H-20/BLA is available to order against an RFQ through our independent distribution channel. Current pricing and stock levels are confirmed at quote time.

What is the datasheet for PALCE610H-20/BLA?

The datasheet covers the PALCE610H family specifications including the 20 ns speed grade, 4.75 V to 5.25 V supply range, and programming algorithm for the electrically erasable PAL architecture.

What is PALCE610H-20/BLA's listed speed (20 ns) on this component line?

The 20 ns propagation delay is the pin-to-pin combinatorial delay at 5 V and 25 °C. This sets the maximum clock frequency for registered outputs and the address-to-output valid time for decode logic.