64 x 5 asynchronous FIFO for 5 V logic pipelines
The 67C4033-15NL is a 64-word by 5-bit asynchronous FIFO in a 20-pin PDIP package, designed for buffering data between two clock domains or bus-width matching in 5 V logic systems. It operates from a 4.5 V to 5.5 V supply and supports a 15 MHz data rate, making it suitable for moderate-speed data transfers in industrial controllers, test equipment, or legacy bus interfaces. The commercial temperature range (0°C to 70°C) fits indoor, non-condensing environments.
Package and mounting — through-hole for prototyping and legacy boards
The 20-pin PDIP is a through-hole package, straightforward to hand-solder and socket. Bulk packaging means parts ship in tubes or trays.
