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AMD (Xilinx) 67C4033-10N — Memory (DRAM / SRAM / Flash / EEPROM)

67C4033-10N FIFO, 64x5 Async, 10MHz, 20-DIP, Active

MPN67C4033-10N
End of Life

67C4033-10N, asynchronous FIFO, 64 x 5 memory depth, 10 MHz data rate, 4.5 V ~ 5.5 V supply, 35 mA max supply current, 0°C ~ 70°C operating temperature, through-hole 20-DIP package.

$21.91Ref. price · indicative, final on quote
Packaging20-DIP
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

67C4033-10N Technical Specifications
ParameterValue
Mounting typeThrough Hole
Expansion typeDepth, Width
Voltage4.5 V ~ 5.5 V
Current - supply35mA
Operating temperature0°C ~ 70°C
PackageBulk
FunctionAsynchronous
Data rate10MHz
Memory size64 x 5
FWFT supportNo
Case20-DIP
Bus directionalUni-Directional
Retransmit capabilityNo
Programmable flags supportNo

Product details

What this FIFO does and where it fits

The 67C4033-10N is an asynchronous FIFO memory with a 64-word by 5-bit organization, designed for narrow-width data buffering in 5 V logic systems. Its 10 MHz data rate supports moderate-speed data transfers between asynchronous clock domains, such as between a slow peripheral and a faster bus. The 64 x 5 depth suits applications like keyboard scan buffers, printer interface staging, or low-resolution ADC data capture where only a few dozen words need temporary storage. The through-hole 20-DIP package fits legacy PCB layouts and prototyping boards.

Expansion and cascading

The 67C4033-10N supports expansion in both depth and width, meaning multiple devices can be cascaded to create larger FIFO arrays. For depth expansion, connect the full-flag output of one device to the write-enable of the next; for width expansion, parallel the control signals across multiple chips. No FWFT (First-Word Fall-Through) or programmable flags are supported, so the flag timing is fixed and must be accounted for in the controller logic.

Package and mounting

Supplied in a 20-pin DIP package (20-DIP body, 20-PDIP footprint), through-hole mounting only. The bulk packaging means parts ship in tubes or trays, not tape-and-reel — plan for manual insertion or wave-solder assembly. Store in dry conditions; the DIP body is not moisture-sensitive but bulk handling can introduce ESD risk.

Temperature grade and environment

Rated for 0°C to 70°C commercial temperature range. Suitable for indoor, temperature-controlled environments like office equipment, test instrumentation, and consumer electronics. Not rated for industrial or automotive extended-temperature operation.

Lifecycle and sourcing

The 67C4033-10N is listed as Active in production, so no immediate last-time-buy pressure. It is RoHS non-compliant, which may restrict use in regions with strict RoHS enforcement unless an exemption applies. Sourced and quoted to order through independent distribution; availability and current pricing confirmed at quote time.

Frequently asked questions

Can 67C4033-10N be used with 3.3V logic?

No, the 67C4033-10N requires a 4.5 V to 5.5 V supply and uses 5 V logic thresholds. It is not compatible with 3.3 V logic without external level translation.

How to cascade 67C4033-10N for deeper FIFO?

The 67C4033-10N supports depth expansion. Connect the full-flag output of the first device to the write-enable input of the next device in the chain. Width expansion is also supported by paralleling control signals across multiple chips.