50 MHz MEMS oscillator with CMOS output
The ASEMPC-50.000MHZ-LY-T3: The enable/disable function allows the output stage to be placed in high-impedance mode, drawing 26 mA maximum in the disabled state versus 35 mA active — a meaningful margin for power-gated clock trees in multi-clock FPGA or SoC designs.
±10 ppm across the industrial temperature band
Frequency stability of ±10 ppm over -40°C to 85°C covers the bulk of industrial and instrumentation timing budgets without requiring tighter compensation grades — for a 50 MHz reference, that ceiling translates to ±500 Hz total deviation across the full operating range, which satisfies most SPI clock, UART baud-rate, and Ethernet reference requirements at this frequency.