Logic level reference
Typical input/output thresholds for TTL, 74HCT, 5 V CMOS, LVTTL, LVCMOS, RS-485 and LVDS — plus a driver-to-receiver compatibility check that verifies VOH ≥ VIH and VOL ≤ VIL with the noise margins spelled out.
Logic family input/output thresholds — typical datasheet values
| Family | VOH | VIH | VIL | VOL |
|---|---|---|---|---|
| TTL (5 V) | 2.4 V | 2 V | 0.8 V | 0.4 V |
| 74HCT (5 V) | 4.9 V | 2 V | 0.8 V | 0.1 V |
| 5 V CMOS (74HC) (5 V) | 4.9 V | 3.5 V0.7·VCC | 1.5 V0.3·VCC | 0.1 V |
| LVTTL (3.3 V) | 2.4 V | 2 V | 0.8 V | 0.4 V |
| LVCMOS 3.3 V (3.3 V) | 3.1 V | 2 V | 0.8 V | 0.2 V |
| LVCMOS 2.5 V (2.5 V) | 2.3 V | 1.7 V | 0.7 V | 0.2 V |
| LVCMOS 1.8 V (1.8 V) | 1.35 V | 1.17 V0.65·VCC | 0.63 V0.35·VCC | 0.45 V |
| RS-485 | differential — A−B high ≥ +1.5 V typ (min +0.2 V); receiver threshold +0.2 / −0.2 V; low ≤ −1.5 V typ | |||
| LVDS | differential — Driver VOD 0.25–0.45 V (typ 0.35) — worst-case 0.25 / −0.25; receiver threshold ±0.1 V; common mode ≈ 1.2 V | |||
Typical JEDEC-style values for reference. Actual thresholds vary by part, temperature and supply — always check the specific datasheet. The differential families are quoted as the A−B voltage (RS-485) or the differential output voltage VOD (LVDS).
Driver → receiver compatibility check
Verdict
VOH ≥ VIH and VOL ≤ VIL
High margin (VOH − VIH)
2.4 V − 3.5 V
Low margin (VIL − VOL)
1.5 V − 0.4 V
Not compatible — VOH 2.4 V is below the receiver VIH of 3.5 V (high state fails). Use a level shifter.
Noise margin
High-state noise margin
Family self-margin: VOH − VIH
Low-state noise margin
Family self-margin: VIL − VOL
The self-margin shows how far a logic output can be pushed before the same family's own input stops reading it. The pair check above compares two different families, which is the margin that matters when mixing TTL, CMOS and LVCMOS on one bus.
About logic levels
A logic family is only as interoperable as its thresholds: the driver must push above the receiver's VIH for a reliable high and pull below its VIL for a reliable low. Classic TTL, with a 2.4 V VOH, cannot drive the 3.5 V VIH of 5 V CMOS directly — the classic reason level shifter ICs exist. Keeping one family for an entire rail, or checking the margin like above, avoids the intermittent glitches that marginal interfaces produce.
For the parts themselves: level shifters and logic gate ICs carry the exact thresholds this check assumes.
Browse related parts:
Frequently asked questions
Is TTL compatible with 5 V CMOS?
No, not directly. TTL drives a guaranteed high of VOH = 2.4 V, but a 5 V CMOS input needs VIH = 3.5 V (0.7·VCC), so the TTL high is 1.1 V short of what the CMOS receiver requires. The tool flags this as not compatible; a level shifter, an open-collector pull-up, or a TTL-compatible CMOS family such as 74HCT (VIH = 2.0 V) is the usual fix.
How is logic compatibility checked?
The check compares the driver output thresholds against the receiver input thresholds: the high state works when VOH(driver) ≥ VIH(receiver) and the low state works when VOL(driver) ≤ VIL(receiver). If both hold the pair is OK; if either margin is under 0.1 V it is flagged marginal; otherwise it is not compatible and the tool names the exact threshold that fails.
What is a noise margin?
The high-state noise margin is VOH − VIH and the low-state is VIL − VOL — how far the output can be dragged by crosstalk, ground bounce or supply droop before the receiver misreads it. The tool shows both the single-family self-margin and the cross-family margin of the driver/receiver pair you selected.
How do RS-485 and LVDS compare to single-ended logic?
They are differential, so thresholds are quoted on the A−B difference instead of against a supply rail. RS-485 drives the line to at least +0.2 V above B for a high (typ +1.5 V) and the receiver decides at ±0.2 V. LVDS drives a 0.25–0.45 V differential output (typ 0.35 V) centred near a 1.2 V common mode, with the receiver sensing ±0.1 V. Both reject ground noise much better than single-ended levels.
Worked example
Drive a 5 V CMOS input from an LVCMOS 3.3 V gate: LVCMOS 3.3 V pushes a VOH of 3.1 V against the CMOS VIH of 3.5 V — the high state fails, so the tool says not compatible. Now drive a classic TTL input from the same LVCMOS 3.3 V output: VOH 3.1 V ≥ VIH 2.0 V and VOL 0.2 V ≤ VIL 0.8 V, with margins of 1.1 V and 0.6 V — the pair is OK. The same table explains why 74HCT exists: TTL-level inputs (VIH 2.0 V) with CMOS output drive (VOH 4.9 V) give a 2.9 V high margin on a 5 V rail.
Thresholds are typical JEDEC-style values; actual parts vary by vendor, temperature and supply tolerance. ICBOMS provides this tool for reference only.