Octal transparent latch for 5V address/data buses
The IDT74FCT2373TQ is an 8-bit D-type transparent latch with tri-state outputs, part of Renesas' FCT logic family. It holds eight bits of data when the latch-enable (LE) signal goes low, while the output-enable (OE) pin controls the bus connection — the tri-state outputs float when OE is high, allowing multiple devices to share the same data bus without contention. Running on a 4.75V to 5.25V supply rail, this is a classic 5V logic part — not compatible with 3.3V or lower-voltage buses without a level translator. The 13ns propagation delay sets the timing window for address latching in a memory or peripheral interface; a 5V bus running at 25 MHz has a 40 ns cycle, so the latch adds about one-third of the cycle in propagation overhead. Output drive is rated 15 mA source, 12 mA sink — enough to drive standard TTL inputs on a backplane or a bank of LEDs through a series resistor, but not intended for high-current loads like relays or motors.
48-pin DIP — through-hole legacy footprint
Housed in a 48-DIP (0.600-inch row spacing, 15.24 mm) through-hole package, this latch is designed for boards that still use plated-through-hole assembly — common in industrial control cards, test equipment, and military/aerospace systems where SMD rework is impractical. The 48-PDIP supplier package code confirms the same body: 0.100-inch pin pitch, 24 pins per side.
Active lifecycle, RoHS non-compliant
The part is RoHS non-compliant, meaning the leads and internal terminations contain lead (Pb) above the exemption threshold. This limits its use to RoHS-exempt categories (military, aerospace, medical implant, industrial control with a 2024+ exemption expiry) or legacy BOMs that already have a lead-bearing waiver.