18-bit bus-interface register in TVSOP-56
The Renesas IDT74FCT162823BTPV is an 18-bit D-type register built on the FAST FCT logic family. It packages two 9-bit elements in a single 56-pin TVSOP body (4.40 mm width) for surface-mount assembly. Each element captures data on the positive edge of the clock and drives the bus through tri-state, non-inverted outputs. The 24 mA symmetric output drive handles moderate capacitive loads on short backplane or memory-interface traces.
Timing and supply margins for the BOM
Maximum propagation delay is 15 ns into a 300 pF load at 5 V supply. This sets the data-to-output settling window for the receiving latch — budget the 15 ns plus clock-to-output skew when calculating the bus cycle time. Quiescent current is 500 µA typical; the dynamic draw scales with the output toggle rate and load capacitance. Input capacitance is 3.5 pF per pin — a light load on the upstream driver.
Production status and compliance flag
RoHS compliance is not claimed for this variant — the part is listed as RoHS non-compliant. Verify the board-level assembly requirements before specifying this order code for a lead-free reflow profile.