PCIe reference clock distribution without the PLL
The Renesas 9DML0441AKILFT is a 2:4 fanout buffer for PCI Express reference clocks, accepting two differential HCSL inputs and delivering four HCSL outputs at up to 200 MHz. It contains no PLL — the outputs are a clean, low-jitter copy of the input, with no frequency multiplication or spread-spectrum synthesis. That makes it a fit for PCIe Gen1 and Gen2 root-complex-to-slot clock trees where the reference already meets the jitter spec and you just need to split the signal without adding phase noise.
200 MHz ceiling and the PCIe generation it serves
Rated for a maximum output frequency of 200 MHz, this buffer covers the 100 MHz reference clock used by PCIe Gen1 and Gen2, plus any 125 MHz or 200 MHz non-PCIe differential clocks in the system. It does not support the 400 MHz references that Gen3 and Gen4 PLL-based buffers handle — if your design targets Gen3 or later, you need a part with a PLL, such as the 9DB803DFLFT (1:8, 400 MHz, PLL-based).
Industrial temperature range — wider than the typical PCIe buffer
Package and supply — standard PCIe footprint
Supply voltage is 3.3 V ±5% (3.135 V to 3.465 V), the standard PCIe clock buffer rail.