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Renesas Electronics 71V3558S133PFGI — DC-DC Power Modules
Renesas Electronics

71V3558S133PFGI 4.5Mbit Synchronous SRAM, 133 MHz, 4.2 ns

MPN71V3558S133PFGI
End of Life

Renesas 71V3558S133PFGI, 4.5Mbit Synchronous SRAM (ZBT), 256K x 18, 133 MHz clock, 4.2 ns access, Parallel interface, 3.135V-3.465V supply, -40 to 85°C, 100-TQFP (14x14), Active.

$5.93Ref. price · indicative, final on quote
71V3558S133PFGI datasheet
Packaging100-LQFP
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications

71V3558S133PFGI Technical Specifications
ParameterValue
Memory typeVolatile
Mounting typeSurface Mount
Voltage3.135V ~ 3.465V
Frequency133 MHz
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageBulk
TechnologySRAM - Synchronous, SDR (ZBT)
Access time4.2 ns
Memory size4.5Mbit
Memory formatSRAM
Case100-LQFP
Memory organization256K x 18

Product details

What this synchronous SRAM brings to the bus

The Renesas 71V3558S133PFGI is a 4.5 Mbit synchronous SRAM organized 256K x 18, built on a ZBT architecture. It clocks at 133 MHz with a 4.2 ns access time. Supply range is 3.135 V to 3.465 V. The industrial temperature grade is -40°C to 85°C.

Package and footprint — what the 100-TQFP demands

The part ships in a 100-lead LQFP (also specified as 100-TQFP) with a 14x14 mm body.

Lifecycle and sourcing reality

For a BOM line that needs a synchronous SRAM at this density and speed grade, there's no LTB clock ticking.

Frequently asked questions

What is the access time of the 71V3558S133PFGI?

The access time is 4.2 ns. Combined with the 133 MHz clock rate, this gives about 3.3 ns of timing margin for setup and hold in a typical synchronous memory controller design.

What package does the 71V3558S133PFGI come in?

It comes in a 100-lead LQFP (also specified as 100-TQFP) with a 14x14 mm body — a fine-pitch surface-mount package that requires careful PCB layout for 133 MHz signal integrity.

What is the memory organization of the 71V3558S133PFGI?

It is organized as 256K words by 18 bits (4.5 Mbit total). The 18-bit width is typical for designs that need a parity or ECC bit per 16-bit word, or for 9-bit byte-oriented datapaths.