25 ns access in a legacy 28-DIP footprint
The 71256SA25TPG is a 256Kbit asynchronous SRAM organized as 32K x 8, with a 25 ns access time that sets the bus-cycle ceiling for a 5 V logic system. In a 28-pin DIP (0.300" body), this is the through-hole parallel memory for designs that need a drop-in replacement or a new build on a legacy board where the PLCC or SOJ footprint is not an option.
Write cycle and bus timing
The write cycle time equals the 25 ns access time — word or page mode — so the memory keeps up with a 40 MHz bus without wait states on back-to-back writes.
