Tri-core architecture — what it buys you
The LPC4370FET100K runs a 32-bit ARM Cortex-M4 for DSP/number-crunch paired with two Cortex-M0 cores for peripheral and communications offload. At 204 MHz the M4 handles the control loop or audio processing while the M0s manage Ethernet, CAN, USB, and the EBI/EMI bus without stealing cycles. That asymmetric multiprocessing is the main reason to pick this over a single-core MCU in the same BGA footprint.
Memory and I/O — what's on board
282K x 8 SRAM is the only internal memory; no Flash is on-chip. Code must execute from external memory via the EBI/EMI or SPI interface.