120 MHz Cortex-M3 — what it means for throughput
The 120 MHz core clock is the highest in the LPC17xx value line, giving this part enough margin for real-time control loops running alongside communication stacks. If your application needs to handle a CANopen fieldbus, a USB host stack, and a motor PWM update all within the same interrupt window, the 120 MHz clock keeps the bus turnaround tight.
Memory sizing for the BOM
512 KB Flash is enough for a moderate firmware image — a FreeRTOS kernel, a USB stack, and a CANopen node fit without squeezing. The 96 KB RAM handles packet buffers and data logs; if your design runs a graphical display or large lookup tables, check whether the RAM budget covers the frame buffer. The on-chip 4 KB EEPROM saves an external serial EEPROM for calibration constants or boot counters.
Connectivity and I/O count
USB OTG lets the MCU act as either host or device — useful for direct flash-drive logging or firmware updates from a laptop. The CAN controller targets industrial automation and vehicle networks. With 165 I/O pins, you can route a parallel LCD, an external SRAM or NOR Flash bus, and still have pins left for pushbuttons and LEDs.