NXP LPC1517JBD64Y — 72 MHz ARM Cortex-M3 MCU, 64KB Flash, 3.3 V, 64-LQFP
NXP LPC15xx series ARM Cortex-M3 MCU, 72 MHz, 64KB Flash, 12KB SRAM, 4KB EEPROM, CAN/I²C/SPI/UART, 46 I/O, 2.4–3.6 V, -40°C to 105°C, 64-LQFP (10×10 mm) tape-and-reel.
- 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
- Date & lot codes on quoteStated per line before you commit; label photos on request.
- MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
- PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.
Specifications
| Parameter | Value |
|---|---|
| Series | LPC15xx |
| Mounting type | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 2.4V ~ 3.6V |
| Operating temperature | -40°C ~ 105°C (TA) |
| Speed | 72MHz |
| Package | Tape & Reel (TR) |
| RAM size | 12K x 8 |
| Core size | 32-Bit Single-Core |
| EEPROM size | 4K x 8 |
| Peripherals | Brown-out Detect/Reset, DMA, POR, PWM, WDT |
| Connectivity | CANbus, I²C, SPI, UART/USART |
| Number of i (O) | 46 |
| Core processor | ARM® Cortex®-M3 |
| Case | 64-LQFP |
| Data converters | A/D 24x12b |
| Program memory size | 64KB (64K x 8) |
Frequently asked questions
What supply voltage does the LPC1517JBD64Y need, and is the brown-out detect spec'd for a ±10 % rail tolerance?
The part operates from 2.4 V to 3.6 V, designed around the 3.3 V nominal rail. Brown-out detect and reset is integrated on-chip. The reset voltage window is guaranteed across the full -40°C to 105°C temperature range — verify the specific threshold levels against your rail tolerance in the NXP datasheet.
How many of the 46 I/O are available for simultaneous use of CAN, SPI, I²C, and UART?
All four peripheral interfaces are available on the LPC1517JBD64Y, but the 46 pins are shared across functions through pin-muxing. Whether a full set of each is simultaneously usable depends on the specific pin assignment in your firmware — check the mux table to confirm no pin-sharing conflict for your combination of active peripherals.