Memory split: Flash, EEPROM, and RAM
The 32 KB Flash (32 K × 8) is sized for a moderate firmware image — bootloader, a real-time control loop, and a communication stack fit without squeezing. The 4 KB EEPROM (4 K × 8) is the key differentiator versus the base LPC11xx parts: it stores calibration constants, node ID, or fault logs without wearing the Flash. The 10 KB SRAM (10 K × 8) supports a few hundred bytes of stack plus a modest data buffer for a UART or I²C transaction. If the application needs a large frame buffer or a TCP/IP stack, the RAM will be the binding constraint.
The part includes I²C, SPI/SSI/SSP, and UART/USART blocks, plus a Microwire interface.
