50 MHz — what it buys on a CAN bus
At 50 MHz the Cortex-M0 core can run a CANopen protocol stack while servicing the 8-channel 10-bit ADC and a UART. The 8 KB SRAM is tight for large buffers.
It remains available for new BOM placements.

NXP LPC11Cxx series 32-bit ARM Cortex-M0 MCU, LPC11C22FBD48/301, 50 MHz, 16KB Flash, 8KB SRAM, integrated CAN 2.0B, 48-LQFP, -40 to 85 °C.
| Parameter | Value |
|---|---|
| Series | LPC11Cxx |
| Mounting | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 1.8V ~ 3.6V |
| Operating temperature | -40°C~85°C(TA) |
| Speed | 50MHz |
| Package | Tray |
| RAM size | 8K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | Brown-out Detect/Reset, POR, WDT |
| Connectivity | CANbus, I²C, Microwire, SPI, SSI, SSP, UART/USART |
| Number of i (O) | 36 |
| Core processor | ARM® Cortex®-M0 |
| Case | 48-LQFP |
| Data converters | A/D 8x10b |
| Program memory size | 16KB (16K x 8) |
At 50 MHz the Cortex-M0 core can run a CANopen protocol stack while servicing the 8-channel 10-bit ADC and a UART. The 8 KB SRAM is tight for large buffers.
It remains available for new BOM placements.
Within the LPC11Cxx family, the LPC11C24FBD48/301, offers 32 KB Flash and 10 KB SRAM in the same 48-LQFP footprint, which is useful when the firmware outgrows the 16 KB limit. Pin compatibility is maintained across the density options in this series.
The core runs at 50 MHz, which is the maximum CPU clock for the LPC11Cxx series.