NXP LPC1100L series 32-bit ARM Cortex-M0 MCU, LPC1113FHN33/302551, 50 MHz core, 24 KB Flash, 8 KB RAM, 28 I/O, I²C/SPI/UART, 8-channel 10-bit ADC, -40°C to 85°C, 32-HVQFN exposed pad.
| Parameter | Value |
|---|---|
| Series | LPC1100L |
| Mounting | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 1.8V ~ 3.6V |
| Operating temperature | -40°C~85°C(TA) |
| Speed | 50MHz |
| Package | Bulk |
| RAM size | 8K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | Brown-out Detect/Reset, POR, WDT |
| Connectivity | I²C, SPI, UART/USART |
| Number of i (O) | 28 |
| Core processor | ARM® Cortex®-M0 |
| Case | 32-VQFN Exposed Pad |
| Data converters | A/D 8x10b |
| Program memory size | 24KB (24K x 8) |
The UART/USART, SPI, and I²C interfaces cover the common serial protocols for sensor readout, display communication, or programming through a bootloader.
The base number LPC1113 covers multiple Flash and RAM density options in the same package, so if a future BOM revision needs more memory, a pin-compatible sibling in the LPC111x family can be swapped without a PCB change.
The LPC111x family includes multiple Flash and RAM density options in the same 32-HVQFN footprint. A pin-compatible sibling with higher memory (e.g., 32 KB or 64 KB Flash) can be substituted without a PCB layout change, though firmware must be recompiled for the larger memory map.
The core runs at 50 MHz, which is the maximum clock for this ARM Cortex-M0 implementation in the LPC1100L series.