50 MHz Cortex-M0 — throughput for the class
At 50 MHz the Cortex-M0 delivers roughly 50 DMIPS, enough to handle a UART protocol stack, poll a few ADC channels, and toggle GPIO without timing pressure. For a part in this memory tier, the speed is well matched to the Flash wait-state budget — no wasted cycles on fetch stalls.
Peripherals and I/O
27 GPIO lines, I²C, SPI, and UART/USART serial interfaces, plus a 6-channel 8-bit ADC.
NXP lists the LPC1112LVFHI33/103 as Active. No last-time-buy notice or phase-out date is on record.