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Analog Devices MAX9601EUP+T — Logic ICs

MAX9601EUP+T Analog Devices Comparator, 0.5ns, 20-TSSOP

MPNMAX9601EUP+T
End of Life

Analog Devices MAX9601EUP+T dual comparator with latch, 0.5ns propagation delay, 30mV hysteresis, PECL complementary outputs, 20-TSSOP package, Tape & Reel.

$13.42Ref. price · indicative, final on quote
Packaging20-TSSOP (0.173", 4.40mm Width)
StockContact for availability
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

MAX9601EUP+T Technical Specifications
ParameterValue
Typewith Latch
Output typeComplementary, Differential, PECL
Mounting typeSurface Mount
Voltage - input offset5mV @ -5.2V, 5V
Current - output50mA
Current - quiescent27mA
Current - input bias6µA @ -5.2V,5V
Operating temperature-40°C ~ 85°C
PackageTape & Reel (TR); Cut Tape (CT)
Hysteresis30mV
Case20-TSSOP (0.173\", 4.40mm Width)
CMRR, PSRR70dB CMRR, 65dB PSRR
Number of elements2
Propagation delay0.5ns

Product details

Active production — dual comparator with latch

The MAX9601EUP+T: The 30mV internal hysteresis eliminates output chatter on slow-moving inputs without external feedback resistors, simplifying the layout around the 20-TSSOP package.

PECL outputs and signal integrity

Complementary, differential PECL outputs drive 50mA typical into terminated transmission lines — the differential swing keeps noise immunity high in a backplane or cable interconnect where ground potential shifts between cards.

Quiescent budget and input bias

Maximum quiescent current is 27mA per device — the two comparators together draw under 54mA from the ±5V rails, leaving headroom for the upstream driver and downstream logic on the same supply. Input bias current maxes at 6µA at the rated supply voltages (-5.2V, 5V), which sets the source impedance ceiling for the driving stage — a 1kΩ source contributes 6mV of additional offset, equal to the input offset spec itself.

20-TSSOP body (4.40mm width) with 0.65mm pin pitch — the narrow pitch demands a controlled-impedance PCB stack-up if the PECL outputs route more than a few centimetres; the exposed paddle (if present on the thermal pad variant) should be connected to the ground plane for heat sinking. CT works for prototype or low-quantity builds.

Frequently asked questions

What is the MAX9601EUP+T's propagation delay and why does it matter?

Maximum propagation delay is 0.5ns. This sets the timing budget for latching a comparison result within a single clock cycle at clock rates up to roughly 2 GHz — above that, the delay plus output rise time consumes the entire period.