PLL clock driver for 3G, Ethernet, and SONET/SDH
The MAX9450EHJ is a PLL-based clock driver from Maxim Integrated, designed to clean up and distribute reference clocks in high-speed communications equipment. It accepts LVCMOS, LVDS, or LVPECL inputs and delivers a single LVPECL output pair, with a 2:2 input-to-output ratio. The on-chip PLL reduces jitter and aligns the output phase to the selected input, making it suitable for 3G base stations, Ethernet switches, and SONET/SDH line cards.
Input flexibility, fixed output format
The MAX9450EHJ accepts three input standards — LVCMOS, LVDS, and LVPECL — so it can interface with a crystal oscillator, a previous-stage PLL, or a differential clock source without external level translation. The output is fixed to LVPECL, the standard for driving high-speed clock lines over short PCB traces. If your downstream logic needs LVDS or HSTL, you'll need a translator or a different clock driver.
The PLL's jitter performance will degrade at the temperature extremes — expect a few picoseconds of added jitter at 85°C — but the part stays within spec for the listed applications.