Dual comparator with latch in 14-SOIC
The MAX9202ESD+ is a dual comparator with a latch function, meaning it holds the output state when the latch is enabled — useful for sampling and holding a comparison result in a noisy environment. Outputs are TTL-compatible, so they drive logic inputs directly without a level translator — a clean fit for a 5V logic bus.
Parametric fit for signal-chain designs
Typical CMRR and PSRR are both 86.02 dB, giving it solid rejection of common-mode and supply noise — relevant when the comparator sits near a switching regulator or motor drive. Maximum input offset voltage is 4 mV at ±5V, and maximum input bias current is 5 µA at ±5V — these set the threshold accuracy floor for low-level signal detection. Quiescent current maxes at 4 mA, 3 mA, or 1.5 mA depending on the supply configuration — the 1.5 mA figure applies to the dual-supply case, keeping the thermal budget low in a 14-SOIC footprint.