Reset timing and output drive
The 140 ms minimum reset timeout gives downstream devices — MCUs, FPGAs, or ADCs — enough time to stabilize after power-up before the reset is released. Active-low reset is the standard for most processor reset inputs, so this part drops into existing designs without level translation.
RoHS non-compliance is noted — verify your assembly line's exemption policy if this part is going into a lead-free process. For new designs requiring RoHS compliance, check the lead-free variant suffix.